This invention relates generally to segment management in a computer virtual memory system, and more specifically to reducing the memory and processing required for managing virtual memory segments by overloading the use of existing page table entries in a virtual memory page table.
Existing virtual memory management systems implement various schemes for keeping track of which virtual memory segments are mapped to which physical pages of working (physical) memory. These systems require the allocation of additional memory for “bookkeeping” data structures to keep track of these virtual and physical memory address mappings.
Certain terms are commonly used in the field of virtual memory segmentation, including a “page” which is defined as a set of bytes in working/physical memory aligned to a specific byte boundary. On the Advanced RISC Machine (ARM) architecture, a set of 4096 (4K) bytes aligned to a 4 K byte boundary is a standard-sized page, there can also be large pages (e.g., 64K). A virtual memory “segment” is one or more consecutive pages mapped into a virtual memory range. A “range” is a portion of the total virtual memory address space which is a multiple of 1 MB in size, and which starts on a 1 MB boundary. A “page table” (PT) on an ARM is a set of 256 consecutive page table entries. Each page table is 1024 (1K) bytes in size. Multiple page tables can exist contiguously, or scattered, in memory. A “page table entry” (PTE) is a descriptor which contains the physical memory address for a page, along with flag bits describing the permissions and caching that should be used when accessing that page. On the ARM architecture each PTE is exactly one word (32 bits) in size. A “memory management unit” (MMU) is the portion of a computer architecture that interprets the page table entries and uses them to translate virtual memory addresses to physical memory addresses. A “page index” is a page number within a given range, such that multiplying the page index by the page size (e.g., 4096) and adding the resulting product to the base address for the range, will yield a valid virtual memory address.
All of virtual memory (e.g., 4 GB on an ARM) is divided up into ranges, which describe regions (e.g., 1 MB or more) of memory, defined in multiples of the range base size (e.g., 1 MB). Within each range, there can be multiple segments (e.g., 4K or more) of virtual memory, defined in multiples of the segment base size (e.g., 4K). As mentioned above, a page table consists of a series of page table entries (PTEs) that indicate the physical memory addresses and permissions for the pages that correspond to each virtual memory address. Within the page table there are a mix of PTEs corresponding to allocated and free segments. A free segment means that the span of virtual memory addresses is available, and has no direct correlation to physical memory addresses.
Virtual memory segment management processes use the above-described data structures in order to perform memory (virtual-physical) translation operations.